Even though I see a graph of how memory accesses have gotten slower relative to everything else at every conference I attend, it's still striking to see how much relative cycle times have changed. IN and OUT are now serializing instructions that have a penalty of hundreds of clocks, not even including time spent waiting for the I/O itself, as they flush the machine or cause some scheduled instructions to replay, depending on whether or not your micro-architecture supports dependent replay. The memory access instructions aren't quite so bad, since they might hit in the cache, and they don't create a serializing memory barrier, but they can still be hundreds of cycles.
Correctly predicted branches now have a cost of 1, and almost all branches are correctly predicted (and they're actually free on the P4, if they're already in the trace cache). The arithmetic instructions are now single cycle, too, and multiple copies of them can execute in the same cycle (and they're only half a cycle on early P4 micro-architectures).
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Even though I see a graph of how memory accesses have gotten slower relative to everything else at every conference I attend, it's still striking to see how much relative cycle times have changed. IN and OUT are now serializing instructions that have a penalty of hundreds of clocks, not even including time spent waiting for the I/O itself, as they flush the machine or cause some scheduled instructions to replay, depending on whether or not your micro-architecture supports dependent replay. The memory access instructions aren't quite so bad, since they might hit in the cache, and they don't create a serializing memory barrier, but they can still be hundreds of cycles.
Correctly predicted branches now have a cost of 1, and almost all branches are correctly predicted (and they're actually free on the P4, if they're already in the trace cache). The arithmetic instructions are now single cycle, too, and multiple copies of them can execute in the same cycle (and they're only half a cycle on early P4 micro-architectures).