I was just saying the low end chips have only "little" cores, no "big" cores, but they are still multi-core. AFAIK nobody makes single core Cortex A chips. Single core Cortex M chips are made, but those are really puny.
Hilariously, it is common to see some SoCs, like the i.MX8, have Cortex-A and Cortex-M cores. You can do fun stuff like run different operating systems on them too. They can be used for real-time applications, safety-critical functions, etc..
And by "fun" I mean not-fun, because you've got multiple build processes and releases to manage.
But I think that's not used as a multiprocessor, with threads getting scheduling on either (or both) depending on power policy. The embedded cores are, I think, used as separate systems running separate OS that happen to have access to the same DRAM, like a peripheral that can do DMA.
Thinking of running that as a single multiprocessing system I'm reminded of the bug caused by Samsung doing big.LITTLE with cores that have the same instruction set but differently sized cache lines: https://news.ycombinator.com/item?id=12481700
But I think that's not used as a multiprocessor, with threads getting scheduling on either (or both) depending on power policy. The embedded cores are, I think, used as separate systems running separate OS that happen to have access to the same DRAM, like a peripheral that can do DMA.
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I was just saying the low end chips have only "little" cores, no "big" cores, but they are still multi-core. AFAIK nobody makes single core Cortex A chips. Single core Cortex M chips are made, but those are really puny.
Hilariously, it is common to see some SoCs, like the i.MX8, have Cortex-A and Cortex-M cores. You can do fun stuff like run different operating systems on them too. They can be used for real-time applications, safety-critical functions, etc..
And by "fun" I mean not-fun, because you've got multiple build processes and releases to manage.
But I think that's not used as a multiprocessor, with threads getting scheduling on either (or both) depending on power policy. The embedded cores are, I think, used as separate systems running separate OS that happen to have access to the same DRAM, like a peripheral that can do DMA.
Thinking of running that as a single multiprocessing system I'm reminded of the bug caused by Samsung doing big.LITTLE with cores that have the same instruction set but differently sized cache lines: https://news.ycombinator.com/item?id=12481700
Right, I didn't mean to imply otherwise.
There are variations on this theme where the two types of cores are also cache coherent with each other.