Yeah, this paper is amazing; anyone considering using the IOMMU or interested in performance at the PCIe level should read it.
We can also confirm their result about the IOMMU TLB size of only 64 on the CPUs we have here. (Yes, the TLB size is completely undocumented and there are no performance counters...)
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I actually went straight to one of their references (https://gianniantichi.github.io/files/papers/pciebench.pdf) which was an amazing find. I should keep up more with the academic conferences, I guess.
The most interesting / surprising thing about this paper is how damning it is for the Intel IOMMU.
Yeah, this paper is amazing; anyone considering using the IOMMU or interested in performance at the PCIe level should read it.
We can also confirm their result about the IOMMU TLB size of only 64 on the CPUs we have here. (Yes, the TLB size is completely undocumented and there are no performance counters...)