Modern x86 processors already do a lot of register renaming and speculative and out of order execution. Much of the huge complexity you're worried about already exists in modern CPUs in order to track and eliminate false data dependencies and to keep the CPU busy in the face of data hazards.
I'm well aware of the basics of ooo. What GP was proposing involves re-vectorizing a virtual ISA according to hardware width. I'm sure micro-op fusion and register renaming could theoretically be extended to do that. It's the complexity I was alluding to.
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Modern x86 processors already do a lot of register renaming and speculative and out of order execution. Much of the huge complexity you're worried about already exists in modern CPUs in order to track and eliminate false data dependencies and to keep the CPU busy in the face of data hazards.
I'm well aware of the basics of ooo. What GP was proposing involves re-vectorizing a virtual ISA according to hardware width. I'm sure micro-op fusion and register renaming could theoretically be extended to do that. It's the complexity I was alluding to.