1) You're right. The problem here is the unpredictability of the buffer's size - it's equivalent to halting problem in general. You miss just one item in the buffer and you risk circuit not working at random times.
2) OpenCL->HDL takes hours to complete due to need to synthesize, whereas OpenCL->CPU code takes seconds at worst. The time to get working (synthesized) code is major blocking factor in utilizing FPGAs anywhere.
Comments
1) You're right. The problem here is the unpredictability of the buffer's size - it's equivalent to halting problem in general. You miss just one item in the buffer and you risk circuit not working at random times.
2) OpenCL->HDL takes hours to complete due to need to synthesize, whereas OpenCL->CPU code takes seconds at worst. The time to get working (synthesized) code is major blocking factor in utilizing FPGAs anywhere.