I didn't know about that one. Sounds like a failed implementation of the concept. A better one that someone told me about recently was some embedded products combining a good CPU with a weaker one (eg Cortex M0) that absorbed & queued interrupts to preserve real-time properties. Sandia did something similar in SSP processor. lowRISC is experimenting with their minion cores.
So, I think there's still potential. Especially given the formal verification and security strategies for I/O programs were often different in academic literature than algorithmic ones. Specialized hardware might facilitate improving their security or availability in provable way.
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I didn't know about that one. Sounds like a failed implementation of the concept. A better one that someone told me about recently was some embedded products combining a good CPU with a weaker one (eg Cortex M0) that absorbed & queued interrupts to preserve real-time properties. Sandia did something similar in SSP processor. lowRISC is experimenting with their minion cores.
So, I think there's still potential. Especially given the formal verification and security strategies for I/O programs were often different in academic literature than algorithmic ones. Specialized hardware might facilitate improving their security or availability in provable way.