Skip to content

Comment on Free FPGA: Reimplement the primitives modelsparent

Comments

No single dominating block. Camera has 4 sensor channels (now either 12 bit parallel or Aptina HiSPI) with gamma and histograms, 16-channel DDR3 controller, 4 compressor channels, inter-camera synchronization and high-speed IMU logger. And AHCI SATA2 controller (with provisions to be later upgraded to SATA3). The last module uses 6%, others share other 78% slices. As most of them have 4 identical instances, it makes about 10% each. Years ago one similar channel (1 sensor, 1 compressor, slower clocks) was implemented on Spartan-3e.

AboutSource Built by g1lg1l

Hackerly is an independent reader for Hacker News, built on the public HN API. Not affiliated with Y Combinator.